Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. Emerging variable resistance memories increasingly offer these advantages. Programmable Conductance Random Access Memory (PCRAM) is one example of such a memory. Additionally, Magnetoresistive Random Access Memory (MRAM) technology has been increasingly viewed as offering all these advantages. Other types of variable resistance memories include polymer-based memory and chalcogenide-based memory.
A PCRAM element has a structure including a chalcogenide-based glass region incorporating a metal (or metal ions) and electrodes on either side of the glass region. Information can be stored as a digital “1” or “0” as stable resistance states. A typical chalcogenide glass used in PCRAM devices is GexSe100-x. The chalcogenide glass can also be used in conjunction with layers of Ag and/or Ag2Se. An example of a PCRAM device is described in U.S. Pat. No. 6,348,365 to Moore and Gilton. The glass region of a PCRAM element can be made less resistive upon application of a threshold voltage. This less resistive state is maintained in a non- or semi-volatile manner and is reversible by applying a reversed voltage. The resistance state of a PCRAM element can be sensed by the application of a sub-threshold voltage through the cell element.
A magnetic memory element has a structure which includes ferromagnetic layers separated by a non-magnetic barrier layer that forms a tunnel junction. An example of an MRAM device is described in U.S. Pat. No. 6,358,756 to Sandhu et al. Information can be stored as a digital “1” or a “0” as directions of magnetization vectors in these ferromagnetic layers. Magnetic vectors in one ferromagnetic layer are magnetically fixed or pinned, while the magnetic vectors of the other ferromagnetic layer are not fixed so that the magnetization direction is free to switch between “parallel” and “antiparallel” states relative to the pinned layer. In response to parallel and antiparallel states, the magnetic memory element represents two different stable resistance states, which are read by the memory circuit as either a “1” or a “0.” Passing a current through the MRAM cell enables detection of the resistance states.
As mentioned above, polymer memory, another type of variable resistance memory, utilizes a polymer-based layer having ions dispersed therein or, alternatively, the ions may be in an adjacent layer. The polymer memory element is based on polar conductive polymer molecules. The polymer layer and ions are between two electrodes such that upon application of a voltage or electric field the ions migrate toward the negative electrode, thereby changing the resistivity of the memory cell. This altered resistivity can be sensed as a memory state.
Chalcogenide memory, another type of variable resistance memory, switches resitivity states by undergoing a phase change in response to resistive heating. The two phases corresponding to the two stable resistivity states include a polycrystalline state and an amorphous state. The amorphous state is a higher resistive state, which can be read as stored data.
A problem encountered in variable resistance memory array architectures is the generation of sneak paths. Sneak paths during read operations are most prevalent in cross-point array architectures, and exist wherever memory cells are in direct electrical contact with one another through the array. A sneak path is a parasitic path or logic flow within a system which, under certain conditions, can initiate an undesired function or inhibit a desired function. Typically, in variable resistance memory circuits the problem is exhibited when reading data from a desired cell. Other cells in electrical contact with the addressed cell provide alternate routes for current, causing a sneak path and lowering the memory circuit's resistance to potentially unreadable levels.
A variable resistance memory array 10, in this example an MRAM array, is shown in FIG. 1a. MRAM cells 12 are located and addressed at the intersecting points of bit lines 16 (also called column lines) and word lines 18 (also called row lines). When the cell 12 to be read is addressed by coupling the word line 18 and forcing a current on the bit line 16, the addressed cell 12 exhibits a resistivity based on its programmed state, which can be sensed by sense circuitry 14 coupled to the bit lines 16 and/or word lines 18. However, parasitic current also flows through other non-addressed cells 12a of the array 10 in multiple sneak paths. These sneak paths reduce the total resistivity of the cell 12 being sensed by the sense circuitry 14. With the diminished resistance there is a smaller margin between the programmed higher and lower resistive states of the memory cell 12, making the memory more difficult to read.
Sneak path equivalent resistance, which is an equivalent resistances of the memory cells of the sneak path, provides an alternate route for current in the array architecture when the selected cell 12 is being sensed. Thus, the sneak path creates an effective parallel current path. To minimize the impact of the sneak path an equal potential voltage VA, which is equal to the sensed bit line voltage VA′, is applied to all unselected bit lines 16a, and unselected word lines 18a. Based on the equal potential voltage scheme, FIG. 1b shows the equivalent circuit and resistances between the sensed bit line 16 (e.g., VA′), the forced equal potential VA voltage on the unselected bit lines 16a and word lines 18a, and the grounded word line 18. The resistance R20r between the sensed bit line 16 and unselected bit lines 16a is approximated to be:Rsneak1=R/(r−1),   (1)where R is the average resistance of the MRAM memory cells and r is the total number of word lines 18 or rows in the memory array 10.
The second sneak path resistance R20c is formed through node VA and ground. This resistance is approximated to be:Rsneak2=R/(c−1),   (2)where R is the average resistance of the MRAM memory cells and c is the total number of unselected bit lines 16a or columns in the memory array 10.
Since node VA is forced to a voltage equal to VA′, Rsneak2 will not in the path of the sensing current, and the total equivalent resistance looking from the sense amplifier will not be impacted by Rsneak2. Based on this network the resistance that the sense amplifier 14 connected to bit line 16 will see is calculated to be a function of VA, VA′, R, and Rsneak1 as follows:Rsense=VA′/(((VA′−VA)/Rsneak1)+VA′/R), or   (3)Rsense=R/(((R(VA′−VA)/(Rsneak1*VA′))+1),   (4)where VA′ is the voltage applied to bit line 16 (approximately 0.5 v).
If the difference between VA and VA′ is zero (VA′−VA), then Rsense=R, which is desired, however due to noise, offsets any difference between VA, and VA′ will cause a large reduction in the Rsense value, and the resistance change will be very hard to be sensed.
Noise sensitivity due to the architecture structure and is spread throughout the entire array 10. The resistance change between the two states will result in small input impedance change due to small sneak path resistance, as indicated above. A 20% change in R will result into a very small change in Rsense and will necessitate special biasing circuits as described above (e.g., an equal potential scheme) to increase the Rsense change. For example a 20% resistance change on an average one Mega Ohm resistance and an array with 1000 rows will result in a 1.5% change with 5 mv offset between VA and VA′, 5.8% change with 1 mv between VA and VA′ and 9.0% change with 0.5 mv between VA and VA′.
Therefore, to sense the selected resistive cell in the presence of a noise sneak path that reduces its equivalent sensed resistance change, a special sensing scheme is also required.
An integration sensing scheme is used to amplify the difference above the noise level and then detect the difference between the high resistance programmed state, and low resistance unprogrammed states of the resistive cell. Accordingly, sneak path resistance makes sensing above the noise level more difficult. Thus, it would be advantageous to have a memory array architecture suitable for a variable resistance memory array that could provide similar integration characteristics as a cross-point array architecture, but which would also mitigate the detriments of sneak path occurrence.